1. Field of the Invention
The present invention relates to a device for electrostatic discharge protection, and more specifically to a device for electrostatic discharge protection, which can protect a microchip from electrostatic discharge in fabricating the microchip that operates a high voltage.
2. Discussion of Related Art
One of the basic characteristics that a semiconductor device operating at high voltage must have is that an avalanche breakdown voltage must be higher than an operating voltage. In order to satisfy this characteristic, a N-type MOSFET adopting the drain in which a dopant is diffused twice, as shown in FIG. 1, so-called DDDNMOS (Double Diffused Drain N-type MOSFET) is used as a basic element.
The construction of the DDDNMOS device will now be described with reference to FIG. 1. A plurality of element isolation films 102 are formed in predetermined regions on a semiconductor substrate 101 in which a P well is formed. A gate 103 is formed over the semiconductor substrate 101 between the element isolation films 102. A well pick-up region 104 is formed on the semiconductor substrate 101 between the element isolation film 102sby means of a high-concentration P-type impurity ion implant process. A source active region 105 is formed on the semiconductor substrate 101 between the element isolation film 102 and the gate 103 by means of a high-concentration N-type impurity ion implant process. Furthermore, a drain is formed between the gate 103 and the element isolation film 102 by means of a dual N-type impurity ion implant process. The drain has a drain active region 107 of a high concentration formed within a drain drift region 106 of a low concentration. In this time, the drain active region 107 is formed by implanting an N-type impurity of a sufficient high concentration, e.g., at a dose of 1015 to 1016 cm−2. The drain drift region 106 is formed by implanting an N-type impurity of a concentration lower than that of the drain active region 107, e.g., at a dose of 1013 cm−2. In most cases, since the source active region 105 is formed simultaneously with the drain active region 107 by means of an impurity implant process, the impurity concentration of the source active region 105 is the same as those of the drain active region 107. Furthermore, the P well below the gate 103 constituting a channel is formed by implanting an impurity of a concentration lower than that of the drain drift region 106, e.g., at a dose of 1012 cm−2.
Generally, the lower the impurity concentrations of two regions, which are in contact with each other with an electrically opposite polarity, the higher the avalanche breakdown voltage. Accordingly, if the structure such as the DDDNMOS device is adopted, the impurity concentration of the drain drift region that is in contact with the P well region can be sufficiently lowered. It is thus possible to implement a breakdown voltage of a desired degree.
In order for a DDDNMOS device operating at high voltage to be used as a device for ESD protection, the gate 103, the source 105 and the well pick-up region 104 are all connected to a ground line Vss, and the drain 107 is connected to a power line or an individual I/O pad, as shown in FIG. 2. In a GG_DDDNMOS (Gate Grounded DDDNMOS) having the electrodes constructed as above, if a voltage applied to the drain 107 is lower than a breakdown voltage, current rarely flows. On the contrary, if the voltage applied to the drain 107 is lower than the avalanche breakdown voltage, an impact ionization phenomenon is generated at the boundary where the semiconductor substrate 101 and the drain drift region 106 meet, so that a number of electrical carriers are formed. As a result, a parasitic NPN-BJT (Bipolar Junction Transistor) is formed, and a large amount of current thus flows between the drain 107 and the source 105. Consequently, in the GG_DDDNMOS having the electrodes constructed as above, current rarely flows at a voltage lower than an avalanche breakdown voltage, and current smoothly flows at a voltage higher than an avalanche breakdown voltage. Thus, the GG_DDDNMOS satisfies a basic characteristic that can be used as a device for ESD protection, which can digest undesired stress current in an electrostatic discharge situation and thus protect internal circuits.
Meanwhile, in order to increase the amount of ESD stress current that the device can digest, a GG_DDDNMOS device of a multi-finger structure in which a plurality of the GG_DDDNMOS devices of the single-finger structure as shown in FIG. 2 are connected in parallel, as shown in FIG. 3 is used.
If the parasitic NPN-BJT is formed in the GG_DDDNMOS device and a high current thus starts to flow, there is a characteristic in that an extremely low resistive current path A, which connects the drain, the channel and the source, is formed along the surface of the device, as shown in FIGS. 4(a) and 4(b). Such a surface concentration phenomenon of current serves to degrade the ability of coping with ESD stress current of a GG_DDDNMOS device. More particularly, since electrical resistance of the current path is very low, a thermal breakdown voltage of the GG_DDDNMOS device becomes lower than a BJT triggering voltage. Consequently, there occurs a problem in that stabilized multi-finger triggering is difficult to implement. As such, if the current path is limitedly formed along the surface of the device and current is thus concentrated on the surface of the device, a temperature on the surface of the device sharply increases and a thermal breakdown phenomenon is generated on the surface of the surface accordingly.
It was found through simulation that a temperature in a very limited region on the surface of the boundary of the drain active region 107 and the drain drift region 106 sharply rises to generate a thermal breakdown phenomenon B, as shown in FIGS. 5(a) and 5(b). That is, since current flows on the surface of the surface very limitedly and most of a voltage applied between the drain active region 107 and the source active region 105 is applied on the boundary of the drain active region 107 and the drain drift region 106, a highest temperature region (or thermal breakdown point) is very limited. As such, if the highest temperature region is limitedly distributed at a narrow region, a temperature in the region relatively rapidly rises even a low stress current. Thus, the ability of a device to cope with stress current is lowered.
FIGS. 6(a) and 6(b) show a typical voltage-current characteristic when the GG_DDDNMOS device operates a device for ESD protection. When evaluated in terms of a design window of a device for ESD protection, the GG_DDDNMOS device cannot be used as the device for ESD protection due to the following several problems.
(1) A GG_DDDNMOS device itself is not sufficiently strong against stress current. That is, it could not cope with a sufficient large amount of stress current (Itb≦4 mA/μm).
(2) A GG_DDDNMOS device has a thermal breakdown voltage lower than a BJT triggering voltage (Vtr≧Vtb). Consequently, since each finger does not uniformly operates in a multi-finger structure, it is impossible to increase the ability of the GG_DDDNMOS device to cope with ESD stress even if the number of a finger is increased.
Consequently, in order to effectively perform ESD protection of a microchip that operates at high voltage, it is necessary to develop a device for ESD protection, which can solve those problems of the GG_DDDNMOS device while representing a characteristic of a high avalanche breakdown voltage. More particularly, in order to implement this object, there is a need for a method in which concentration of current, which occurs on the surface of a device, can be mitigated so that stress current can be uniformly distributed over the device.